In recent years, as miniaturization of circuit elements and wires mounted on a digital integrated circuit progresses, an integrated circuit comes to have a number of function blocks such as processors and memories called cores. FIG. 15 illustrates an integrated circuit having a number of cores. In FIG. 15, an integrated circuit 1500 has “n” pieces of cores 1501 from core 0 to core n−1. For communications among the cores 1501, an inter-core connecting circuit 1502 is used. The inter-core connecting circuit 1502 is a circuit such as a bus performing data communications among the cores 1501.
The inter-core communication circuit is designed as a synchronous logic circuit that drives an internal element at a rising or trailing transition (clock edge) of a clock signal. However, from the viewpoints of easiness of designing, power consumption and reduction in electromagnetic radiation, attention is being paid to integrated circuit designing using a GALS (Globally Asynchronous, Locally Synchronous) method of constructing the inter-core communication circuit as an asynchronous logic circuit. The asynchronous logic circuit denotes here a logic circuit which controls a storage element in the circuit by using a handshake signal in place of a clock signal.
Also in an asynchronous logic circuit, like in a synchronous logic circuit, a combinational circuit is disposed between flip flops. However, a signal controlling storage of the flip flops is different from that in a synchronous logic circuit. Specifically, in the synchronous logic circuit, a clock signal from the outside is used as a storage control signal to the flip flops. On precondition that the signal reaches all of the flip flops at the same time, a part made by the flip flops and the combinational circuit is designed. A clock signal distributing circuit is designed so that the signal reaches all of the flip flops at the same time. On the other hand, in the asynchronous logic circuit, a storage control circuit generating a storage control signal to flip flops is used. A pair of handshake signals (a request signal and an acknowledge signal) is transmitted/received between the storage control circuits, the storage timing in the flip flops is controlled. The procedure of controlling communications of the handshake signals is called a handshake protocol.
FIG. 16 illustrates a typical configuration example of the asynchronous logic circuit. The asynchronous logic circuit includes three flip flops (FFs) 1610, 1611, and 1612 and three storage control circuits (LCs) 1620, 1621, and 1622 corresponding to the flip flops 1610, 1611, and 1612, respectively. The storage control circuit sends a request signal (R) to the storage control circuit in the posterior stage, and sends an acknowledge signal (A) to the storage control circuit in the anterior stage. The storage control circuit also sends a storage control signal (L) to a corresponding flip flop. In response to the storage control signal (L), the flip flop stores data. In the asynchronous logic circuit, a storage circuit represented by a flip flop and the storage control circuit are dealt as a pair of registers.
FIG. 17 illustrates an example of operation waveforms of the flip flop FF1 (1611) and the storage control circuit LC1 (1621). The flip flop FF1 and the storage control circuit LC1 operate as follows. First, the flip flop FF0 in the anterior stage stores data d0 (D0=d0) and outputs the data d0 to the flip flop FF1. After the flip flop FF0 stores the data d0, the storage control circuit LC0 corresponding to the flip flop FF0 outputs a request signal R0=1 to the storage control circuit LC1 in the next stage.
By receiving the request signal R0=1, the storage control circuit LC1 detects that data has reached the flip flop FF1. The storage control circuit LC1 generates a storage control signal L1=1. The storage control circuit LC1 changes the storage control signal. L1 to L1=1, thereby making the flip flop FF1 store the data d0 (D1=d0). After the flip flop FF1 stores the data d0, the storage control circuit LC1 outputs an acknowledge signal A0=1 to the storage control circuit LC0 in the anterior stage to notify of completion of data storage. The storage control circuit LC0 in the anterior stage receives the notification of completion of data storage (A0=1) and changes the request signal R0 to be output to the storage control circuit LC1 to R0=0 (the request signal is withdrawn). After that, a request to prepare for next data is sent to the flip flop FF1.
After the flip flop FF1 stores the data d0, the storage control circuit LC1 outputs the request signal R1=1 to the storage control circuit LC2 in the next stage to request data storage in the flip flop FF2. The storage control circuit LC2 in the next stage receives the request signal R1=1 from the storage control circuit LC1, generates the storage control signal L2=1, and stores the data d0 into the flip flop FF2. After that, the storage control circuit LC2 outputs the acknowledge signal A1=1 to the storage control circuit LC1 in the anterior stage. The storage control circuit LC1 receives the acknowledge signal A1=1, thereby detecting data storage in the flip flop FF2.
When the storage control circuit LC1 receives the request signal R0=0 from the storage control circuit LC0 in the anterior stage and receives the acknowledge signal A1=1 from the storage control circuit LC2 in the next stage, the storage control circuit LC1 changes the storage control signal L1 to L1=0. When the storage control signal L1 becomes L1=0, the flip flop FF1 enters a state of preparation for the next data. After the flip flop FF1 is prepared for the next data, the storage control circuit LC1 sends the acknowledge signal A0=0 indicative of completion of preparation of the flip flop FF1 to the storage control circuit LC0 in the anterior stage. The storage control circuit LC1 sends the request signal R1=0 requesting preparation for the next data to the storage control circuit LC2 in the next stage.
The storage control circuit LC0 in the anterior stage receives the acknowledge signal A0=0 and stores the next data d1 into the flip flop FF0. The storage control circuit LC2 in the next stage receives the request signal R1=0 and sends the storage control signal L2 to the flip flop FF2 to make the flip flop FF2 prepare for the next data. The storage control circuits LC0 to LC2 perform operation similar to the above also on the data d1 and transfer the data d1 to the flip flops FF1 and FF2. Although the signals shift periodically in the waveform chart of FIG. 17, even when delay occurs at any of the timings in the procedure, the asynchronous logic circuit operates so as to follow the procedure.
In the case of using an asynchronous inter-core communication circuit, it is unnecessary to synchronize clocks among different functional blocks. There is consequently an effect that a clock distribution range can be limited to a narrow range. In addition, the clock frequency of each of the functional blocks can be freely and dynamically set. Therefore, the clock frequency can be lowered to the minimum frequency at which the functional block realizes predetermined operation. When the clock frequency is lowered, the circuit delay can be increased, and the power supply voltage can be also decreased. Since the power consumption is proportional to the product between the square of the power supply voltage and the clock frequency, by using asynchronous inter-core communication circuit among the functional blocks, the power consumption of the integrated circuit can be reduced largely.
Further, in the case of using the asynchronous inter-core communication circuit, timings of driving synchronous cores can be dispersed in time, so that power and electromagnetic radiation can be also reduced. Specifically, since the synchronous cores are driven at the rising or trailing shifts (clock edges) of the clock signal, a large current change occurs immediately after the clock edge. In the case of using the asynchronous logic circuit as the inter-core communication circuit, since the drive timings are different among the cores, the current in the entire integrated circuit can be leveled. As a result, electromagnetic radiation derived from power at the maximum and current change is reduced.